1. Field of the Invention
The present invention relates to a method for forming a MOS transistor on a semiconductor wafer, and more particularly, to a method for forming MOS transistors with a plurality of different types in a dynamic random access memory (DRAM).
2. Description of the Prior Art
A DRAM consists of thousands, or even millions, of memory cells, as well as a logic circuit. Each memory cell includes a MOS transistor and a capacitor, and the logic circuit has a plurality of MOS transistors. The demands of the memory cell and the logic circuit are different, so the MOS transistors in these different regions have different structures, too. However, in order to reduce process steps, the same MOS structure and the same silicide material are used to form the MOS transistors in the two regions in the present DRAM manufacturing method. However, this is now no longer sufficient to meet the demands of the different circuits.
Please refer to FIG. 1 to FIG. 6. FIG. 1 to FIG. 6 are schematic diagrams of the method for forming different types of MOS transistors 60, 62 in a DRAM on a semiconductor wafer 10 according to the prior art. As shown in FIG. 1, the semiconductor wafer 10 includes a silicon substrate 12. There are two areas 26 and 28 positioned on the silicon substrate 12. The region of area 26 is used for a logic circuit of the DRAM, and the region of area 28 is used for memory cells of the DRAM.
In the prior art method, a thermal oxidation process is performed to form a silicon dioxide layer 14 on surface of the silicon substrate 12. A chemical vapor deposition (CVD) process is then performed to deposit a polysilicon layer 16 on the surface of the silicon dioxide layer 14. The polysilicon layer 16 is then doped. A sputter process is then performed to form a titanium nitride layer 18 and a titanium silicide layer 20 on the polysilicon layer 16 in order. A CVD process is then performed to deposit a silicon nitride layer 22 on the surface of the titanium silicide layer 20.
A photoresist layer is coated on the silicon nitride layer 22, and a lithographic process is performed to define the pattern of the gate in the areas 26 and 28. The excess portions of the photoresist layer are then removed, and the residual photoresist 24 as shown in FIG. 1 is used as a hard mask in the subsequent etching process.
As shown in FIG. 2, a dry etching process is performed to remove the portions which are not covered by the photoresist 24 so as to form a gate 30 in the area 26 and two gates 32 in the area 28 on the silicon substrate 12. The photoresist layer 24 is then stripped. Each of the gates 30, 32 includes a gate oxide layer 34, a doped polysilicon layer 36, a titanium nitride layer 38, a titanium silicide layer 40 and a cap layer 42.
As show in FIG. 3, a low pressure CVD process is performed to form a silicon oxide layer 44 on the surface of the silicon substrate 12 and on the surface of the gates 30, 32. An ion implantation process is then performed to form doped regions 46 in the substrate 12 adjacent to the gates 30, 32. The doped regions 46 are used as lightly doped drains (LDD) of the MOS transistors. A CVD process is then performed to deposit a silicon nitride layer 48 on the silicon oxide layer 44 that covers the gates 30, 32 uniformly.
As shown in FIG. 4, an anisotropic dry etching process is performed to remove the silicon nitride layer 48 so as to form spacers 50 on each wall of gates 30, 32. An ion implantation process is then performed to form doped regions 52. The doped regions 52 are used as sources and drains of the MOS transistors. The MOS transistor 60 in the memory cell of DRAM is then completely formed.
As shown in FIG. 5, a silicon nitride layer (not shown) is deposited on the silicon substrate 12. A lithographic process is then performed to cover the area 28. An etching process is performed to remove the silicon nitride layer in the area 26. The residual silicon nitride layer 54 in the area 28, as shown in FIG. 5, is used as a mask in the subsequent process for forming a titanium silicide layer in the area 26. A cleaning process is used to completely remove the residual silicon oxide layer 44 in the area 26 of the silicon substrate 12. A sputtering process is then performed to form a titanium layer 56 and a titanium nitride layer 58 on the semiconductor wafer 10.
As shown in FIG. 6, a rapid thermal process (RTP) is performed to cause the titanium layer 54 react with the silicon atoms in the area 26 of the silicon substrate 12 so as to form titanium silicide layers 64. The residual titanium layer 56 and the residual titanium nitride layer 58 are then removed. The MOS transistor 62 in the logic circuit of DRAM is completely formed.
After the formations of the MOS transistors 60, 62 in the memory region 28 of DRAM and in the logic circuit region 26 of DRAM, other semiconductor processes can subsequently be performed. This may include forming a dielectric layer on the semiconductor, and then forming contact plugs to electrically connect to the MOS transistors 60, 62.
Because the demands of operational speed in the logic circuit of a DRAM are stricter, controlling the resistance of the gate 30 in the MOS transistor 62 becomes the most important aspect of the MOS transistor 62. Conversely, with the reducing semiconductor line width, the primary concerns for the gate 32 in the MOS transistor 60, which is used for a memory cell 28, is keeping the shape of the gate 32 and etching uniformity.
In order to reduce the resistance of the gate 30 in the logic circuit 26, titanium silicide is commonly used as the material for the silicide layer. However, a titanium silicide layer is not easy to etch, making it more difficult to ensure the shape and uniformity of the MOS transistor 60. In another method, the different types of MOS transistors are formed separately. This method, however, requires more complex process steps, and is not good in embedded processes.